UVM Verfication Engineer

Jenrick Commercial
Cambridge, UK
12 Sep 2019
25 Sep 2019
Contract Type
Full Time
- UVM Verification Engineer
- £455 per day
- 10 month contract
- Role based in Cambridge

Working for a global Semiconductor and software design company based in Cambridge we are looking for an experienced UVM Verification Engineer to work on a 10 month contract.

The ideal candidate

- You will need to have extensive experience of designing and implementing verification environments for complex RTL designs.
- You will be well-versed in the use of class based hardware verficiation languages e.g. SystemVerilog or Specman 'e'
- Have detailed knowledge of Verification methodologies such as UVM
- In-Depth understanding of end-to-end verification processes, from test plan creation through to verification closure.
- Understanding of constrained random stimulus, the goals and general usefulness of different types of coverage in hardware, as well as checking methodologies and behavioural functional models.
- Ability to quickly understand and apply complex specification detail.
- Familiarity with Mentor Questasim simulator required. Synopsys VCS & Cadence Incisive nice to have. The system that would be worked by the contractor would be able to run on these simulators.
- Familiarity with GIT.
- Familiarity with AMBA AXI Specifications preferred.

Scope of the project

- UVM based verification of a complex multi unit System IP product.

Similar jobs

Similar jobs