Senior Digital Design Engineer (FPGA)/ASIC)

We Are SSG
Bar Hill
08 Mar 2018
17 Mar 2018
Contract Type
Full Time

Based in Cambridge the Senior Digital Design Engineer will be joining an exciting organisation working on the development of brand new Imaging Technology.

The Senior Digital Design Engineer will be working on the development and implementation of Algorithms and functional blocks for ASIC Synthesis. Other responsibilities will include System integration, debugging and Block Level Verification.

The successful candidate will have a proven background in ASIC / FPGA Design Technologies, along with:

  • VHDL or Verilog
  • Experience with Hardware Synthesis tools
  • Simulation with ModelSIM, VCS and nc-SIM
  • Python and C/C++
  • Algorithm Implementation

The successful candidate will be working with a highly technical team in modern offices (with a range of facilities) and close to a train station. There is an excellent salary on offer, along with share options, please get in touch for more information.

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