Front End ASIC Design

08 Nov 2017
20 Dec 2017
Contract Type
Full Time
Progressive Recruitment are currently seeking an experienced Front End ASIC Digital Design Engineer for a 36 Month contract role. This role is due to commence ASAP.

Digital design engineer is required to take several small blocks through from specification to P&R.

The blocks are in some cases already implemented, but require modifications to support spec changes and testing.

The engineer should have experience of generating and testing relatively simple digital filters using Verilog within the Cadence environment.

Develop testbenches which thoroughly exercise the blocks.

Experience with Octave or Matlab experience would a benefit.

Blocks will be implemented in both gate level format and in Verilog format for

Generate timing constraint files , and be familiar with the P&R flow, and reimulation with SDF back annotation.

Ideally will also have some experience of using Cadence Encounter or VDI synthesis and P&R tools, and in using/developing scripts for these.

Must be able to work independently

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Progressive Recruitment please visit


Progressive Recruitment, a trading division of SThree Partnership LLP Registered office 1st Floor, 75 King William Street, London, EC4N 7BE, United Kingdom Partnership Number OC387148 England and Wales Advertised through Zoek 863bbbec37944d2a9f6c98a324608c7011