Design Verification Engineer - Hertfordshire

MicroTECH Recruitment Ltd
London, South East England
09 Jul 2017
08 Aug 2017
Contract Type
Full Time

We are working with the highest grossing technology company around. A company that have been changing the way the world communicates for many years.

They are building a verification team and are looking for a number of highly skilled and talented engineers with strong experience of verifying complex IP.

Job Summary:

You, as a Verification Engineer, will be responsible for the pre-silicon RTL verification of blocks in low power embedded graphics cores. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, preferably in graphics, and a solid foundation in verification methodology will be leveraged to close testing coverage with high confidence.

Key Qualifications:

  • Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman experience is a plus

  • Expertise with HDL simulators and waveform viewers

  • Experience defining coverage space, writing coverage model, analyzing results

  • Experience working under strict schedule deadlines with the ability to manage multiple priorities

  • Experience with Perl, Shell scripting, Makefiles, TCL a plus

  • Excellent communication skills and ability to collaborate


  • Develop verification plans in coordination with design leads and architects

  • Create and maintain verification test bench components and environments

  • Generate directed and directed random tests Run simulations and debug design and environment issues Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes Create automated verification flows for block verification

  • Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs

  • Work with other block and core level engineers to ensure seamless verification flow.